01 · OPENING THE CASE
A stadium isn't one big room
Yesterday's metaphor: the GPU is a stadium of thousands of workers. Useful, but it hides the interesting part, which is the floor plan. A GPU is not one massive slab of undifferentiated compute. Lift the lid and you find the chip is built the way a mall is built: 46 identical self-contained units, tiled across the silicon. Each unit has its own workers, its own managers, and its own storage. The official name for a unit is a streaming multiprocessor, SM for short, and you'll see those two letters constantly for the rest of this journey.
On an RTX 4070 there are 46 of them. On a 4090, 128. Same design philosophy at different sizes, like the same apartment layout stamped across different floors of a tower.
02 · THE EXPLORABLE
Step inside
Here's the whole chip as a map. Click any SM to step inside it, then click the parts to find out what each one does. Take a minute with this: every term on this schematic is vocabulary you'll use every day from now on.
RTX 4070 · 46 STREAMING MULTIPROCESSORS
THE CHIP
From the outside, an RTX 4070 is 5,888 cores of raw silicon. From the inside, it's 46 identical tiles called streaming multiprocessors (SMs), each a self-sufficient little computer with its own cores, its own schedulers, and its own memory. Click a tile.
schematic, not a die shot · sizes and counts simplified to the numbers that matter for this journey
The anatomy answers yesterday's story directly. The "workers" are the 128 cores. The "managers keeping supply flowing" are the four warp schedulers. And the two storage blocks at the bottom of the schematic are about to become the most important thing on this page.
03 · WHY TILES?
Stamp, don't design
Why build a GPU as 46 copies of the same unit instead of one big bespoke machine? Three reasons, all unglamorous. First, scaling: a faster GPU is literally the same layout with more tiles stamped on, which is why the 4070 and the 4090 feel like siblings rather than different species. Second, manufacturing: smaller repeated units survive production defects better than one giant monolith. Third, and most important for you: the programming model mirrors the hardware. Your work gets chopped into independent chunks, and the chip hands those chunks out to identical SMs. Because every SM is interchangeable, the hardware can schedule without ever asking you anything.
Those chunks have a name, by the way: blocks. The grid-block-thread hierarchy is exactly day 03's subject, and it will make this tile picture click into place.
04 · THE SCHEDULER, PHYSICALLY
Yesterday's story, in silicon
Remember the day 01 argument: the GPU doesn't hide latency for a thread, it ignores it by having thousands of other threads ready. Here is the exact piece of hardware that does this. Each SM is split into four partitions, and each partition has its own warp scheduler sitting above its 32 cores.
Every single clock cycle, each scheduler looks at the warps assigned to it and fires the instruction of one that's ready. If warp A is stalled waiting on memory, the scheduler doesn't wait with it. It runs warp B this cycle, then warp C, and comes back to A once its data arrived. The switch costs nothing. That's the whole trick: latency doesn't disappear, it gets absorbed by occupancy, by having enough warps resident that some are always ready.
A warp is 32 threads that execute this way in lockstep, one instruction across all of them. That number, 32, will explain divergence, occupancy math, and half the performance advice you'll ever hear. Day 04 is all about it.
05 · THE MEMORY LADDER
The rest of the journey, in one table
The last piece of anatomy is storage, and it deserves more than a glance, because this ladder is where GPU performance is actually won and lost. Four rungs, from fastest and smallest to slowest and biggest:
each rung down: bigger and slower, roughly an order of magnitude at a time
Registers are free to read and tiny. Global memory holds everything but makes you wait hundreds of cycles. Every performance problem you'll meet on this journey is some version of the same sentence: the data your kernel needs is on the wrong rung of this ladder. Coalescing (day 07), shared memory (day 08), caches (day 10), and the roofline model (day 11) are all different tools for climbing the ladder less often.
And that's why the anatomy matters. You don't profile "the GPU." You profile how your kernel moves data between 46 SMs and this ladder.
- 01A GPU is tiled SMs. The 4070 has 46 identical streaming multiprocessors, each self-sufficient with cores, schedulers, and storage. More GPU = more tiles.
- 02One SM = 128 cores + 4 warp schedulers + registers + shared memory. The schedulers switch warps every cycle; that is day 01's latency-hiding, in hardware.
- 03Memory is a ladder. Registers, shared, L2, global: each rung down is bigger and roughly an order of magnitude slower. Performance work is ladder management.
Next: day 03 connects this hardware to your code. Grids, blocks, and threads: the three nouns every kernel is written with, and the ones the chip uses to hand work to those 46 tiles.